To test complex devices, test engineers must rely on the vector sets generated by verification engineers. Unfortunately, verification engineers—who work in a software simulation environment—often have ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Functional verification is nearing an inflection point, brought on by rising complexity and the many tentacles that are intermixing it with other disciplines. New abstractions or different ways to ...

Have you ever released a design, even though you were not fully confident that it was completely verified? Well, you are not alone. The pressure of getting to market faster often results in the ...

Apple is helping to promote a new Design Verification Engineering training course designed to help graduates get jobs at Israeli tech firms and startups, by hosting a meetup for course candidates at ...

It is widely accepted that system verification is the most imposing obstacle to meeting time-to-market schedules. Now, the verification process has become even more time-consuming and expensive. These ...

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...

Intel is working on processors featuring the so-called 'Unified Cores' and these CPUs are at least three or four years away, or may be more, based on a new job listing that Intel posted over at ...

People freely interchange the terms “test” and “verification.” It’s understandable when terms like testcase, testbench and device under test (DUT) are in conjunction with different types of ...